View MAX2112CTIT_8632940.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim integrated .com. general description the max2112 low-cost, direct-conversion tuner ic isdesigned for satellite set-top and vsat applications. the ic is intended for 8psk and digital video broadcast (dvb-s2) applications. the max2112 directly converts the satellite signals from the lnb to baseband using a broadband i/q downconverter. the operating frequency range extends from 925mhz to 2175mhz. the device includes an lna and an rf variable-gain amplifier, i and q downconverting mixers, and baseband lowpass filters with programmable cutoff frequency control and digitally controlled baseband variable-gain amplifiers. together, the rf and baseband variable-gain amplifiers provide more than 80db of gain control range. the ic is compatible with virtually all dvb-s2 demodulators. the max2112 includes fully monolithic vcos, as well as a complete fractional-n frequency synthesizer. additionally, an on-chip crystal oscillator is provided along with a buffered output for driving additional tuners and demodulators. synthesizer programming and device configuration are accomplished with a 2-wire serial inter- face. the ic features a vco autoselect (vas) function that automatically selects the proper vco. for multituner applications, the device can be configured to have one of two 2-wire interface addresses. a low-power standby mode is available whereupon the signal path is shut down while leaving the reference oscillator, digital inter- face, and buffer circuits active, providing a method to reduce power in single and multituner applications. the max2112 is the most advanced dbs tuner avail- able today. the low noise figure eliminates the need for an external lna. a small number of passive compo- nents are needed to form a complete dvb-s2 rf front- end solution. the tuner is available in a very small 28-pin thin qfn package. applications directv and dish network dbsdvb-s2 vsats features ? 925mhz to 2175mhz frequency range ? monolithic vco low phase noise: -97dbc/hz at 10khzno calibration required ? high dynamic range: -75dbm to 0dbm ? integrated variable bw lp filters: 4mhz to 40mhz ? single +3.3v ?% supply ? low-power standby mode ? address pin for multituner applications ? differential i/q interface ? i 2 c 2-wire serial interface ? very small 28-pin tqfn package complete, direct-conversion tuner for dvb-s2 applications vtune gndsyn cpout vcc_syn xtal vcobyp sclvcc_bb qdc- addrqdc+ idc- rfin gc1 vcc_lo + iout+qout- vcc_dig gndtune sda 19 17 16 3 5 18 4 6 vcc_vco refout 15 7 gnd iout- 20 2 vcc_rf1 21 idc+ 1 26 24 23 10 12 25 11 13 22 14 27 9 28 8 vcc_rf2 max2112 interface logic and control dc offset correction lpf bw control div2/div4 ep frequency synthesizer qout+ pin configuration/ functional diagram ordering information * ep = exposed paddle. + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max2112cti+ 0? to +70? 28 thin qfn-ep* max2112eti+ -40? to +85? 28 thin qfn-ep* max2112 19-0869; rev 2; 5/10 downloaded from: http:/// available (9$/8$7,21.,7$9$,/$%/(
complete, direct-conversion tuner for dvb-s2 applications absolute maximum ratings dc electrical characteristics (max2112 evaluation kit: v cc = +3.13v to +3.47v, t a = 0? to +70? (max2112cti+), t a = -40? to +85? (max2112eti+), v gc1 = +0.5v (max gain), default register settings except bbg[3:0] = 1011. no input signals at rf, baseband i/os are open circuited.typical values measured at v cc = +3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +3.9v all other pins to gnd.................................-0.3v to (v cc + 0.3v) rf input power: rfin .....................................................+10dbm vcobyp, cpout, xtal, refout, iout_, qout_ , idc_, qdc_ to gnd short-circuit protection...............................10s continuous power dissipation (t a = +70?) 28-pin thin qfn (derated 34.5mw/? above +70?) ...2.75w operating temperature range (max2112cti+) ......0? to +70? operating temperature range (max2112eti+) ...-40c to +85c junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter conditions min typ max units supply supply voltage 3.13 3.3 3.47 v receive mode, bit stby = 0 100 160 supply current standby mode, bit stby = 1 3 ma address select input (addr) digital input voltage high, v ih 2.4 v digital input voltage low, v il 0.5 v digital input current high, i ih 50 ? digital input current low, i il -50 ? analog gain-control input (gc1) input voltage range maximum gain = 0.5v 0.5 2.7 v input bias current -50 +50 ? vco tuning voltage input (vtune) input voltage range 0.4 2.3 v 2-wire serial inputs (scl, sda) clock frequency 400 khz input logic-level high 0.7 x v cc v input logic-level low 0.3 x v cc v input leakage current digital inputs = gnd or v cc ?.1 1 a 2-wire serial output (sda) output logic-level low i sink = 1ma 0.4 v caution! esd sensitive device max2112 2 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications parameter conditions min typ max units main signal path performance input frequency range (note 2) 925 2175 mhz rf gain-control range (gc1) 0.5v < v gc1 < 2.7v 65 73 db baseband gain-control range bits gc2 = 1111 to 0000 13 15 db in-band input ip3 (note 3) +2 dbm out-of-band input ip3 (note 4) +15 dbm input ip2 (note 5) +40 dbm adjacent channel protection (note 6) 25 db v gc1 is set to 0.5v (maximum rf gain) and bbg[3:0] is adjusted to give a 1v p-p baseband output level for a -75dbm cw input tone at 1500mhz 8 noise figure starting with the same bbg[3:0] setting as above, v gc1 is adjusted to back off rf gain by 10db (note 7) 91 2 db minimum rf input return loss 925mhz < f rf < 2175mhz, in 75 system 12 db baseband output characteristics nominal output voltage swing r load = 2k //10pf 0.5 1 v p-p i/q amplitude imbalance measured at 500khz; filter set to 22.27mhz ? db i/q quadrature phase imbalance measured at 500khz; filter set to 22.27mhz 3.5 d eg r ees s i ng l e- e nd ed i/q outp ut im p ed ance real z o , from 1mhz to 40mhz 30 output 1db compression voltage differential 3 v p-p baseband highpass -3db frequency corner 47nf capacitors at idc_, qdc_ 400 hz baseband lowpass filters filter bandwidth range 4 40 mhz rejection ratio at 2 x f -3db 39 db group delay up to 1db bandwidth 37 ns ratio of in-filter-band to out-of-filter-band noise f inband = 100hz to 22.5mhz, f outband = 87.5mhz to 112.5mhz 25 db frequency synthesizer rf-divider frequency range 925 2175 mhz rf-divider range (n) 19 251 refer ence- d i vi d er fr eq uency rang e 12 30 mhz reference-divider range (r) 1 1 phase-detector comparisonfrequency 12 30 mhz voltage-controlled oscillator and lo generation guaranteed lo frequency range 925 2175 mhz f offset = 10khz -97 f offset = 100khz -100 lo phase noise f offset = 1mhz -122 dbc/hz ac electrical characteristics(max2112 evaluation kit: v cc = +3.13v to +3.47v, t a = 0? to +70? (max2112cti+), t a = -40? to +85? (max2112eti+), default register settings except bbg[3:0] = 1011. typical values measured at v cc = +3.3v, t a = +25?.) (note 1) max2112 maxim integrated 3 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications ac electrical characteristics (continued)(max2112 evaluation kit: v cc = +3.13v to +3.47v, t a = 0? to +70? (max2112cti+), t a = -40? to +85? (max2112eti+), default register settings except bbg[3:0] = 1011. typical values measured at v cc = +3.3v, t a = +25?.) (note 1) parameter conditions min typ max units xtal/reference oscillator input and output buffer xtal oscillator frequency range parallel-resonance-mode crystal (note 8) 12 30 mhz input overdrive level ac-coupled sine-wave input 0.5 1 2.0 v p-p xtal output-buffer divider range 1 8 xtal output voltage swing 4mhz to 30mhz, c load = 10pf 1 1.5 2 v p-p xtal output duty cycle 50 % note 1: max2112cti+: min/max values are production tested at t a = +70?. min/max limits at t a = 0? and t a = +25? are guaranteed by design and characterization.max2112eti+: min/max values are production tested at t a = +85?. min/max limits at t a = -40? and t a = +25? are guaranteed by design and characterization. note 2 : input gain range specifications met over this band. note 3 : in-band iip3 test conditions: gc1 set to provide the nominal baseband output drive when mixing down a -23dbm tone at 2175mhz to 5mhz baseband (f lo = 2170mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -26dbm each are applied at 2174mhz and 2175mhz. the im3 tone at 3mhz is measured at baseband, but is referred to therf input. note 4 : out-of-band iip3 test conditions: gc1 set to provide nominal baseband output drive when mixing down a -23dbm tone at 2175mhz to 5mhz baseband (f lo = 2170mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -20dbm each are applied at 2070mhz and 1975mhz. the im3 tone at 5mhz is measured at baseband, but is referred to therf input. note 5 : input ip2 test conditions: gc1 set to provide nominal baseband output drive when mixing down a -23dbm tone at 2175mhz to 5mhz baseband (f lo = 2170mhz). baseband gain is set to its default value (bbg[3:0] = 1011). two tones at -20dbm each are applied at 925mhz and 1250mhz. the im2 tone at 5mhz is measured at baseband, but is referred to the rf input. note 6 : adjacent channel protection test conditions: gc1 is set to provide the nominal baseband output drive with a 2110mhz 27.5mbaud signal at -55dbm. gc2 set for mid-scale. the test signal shall be set for pr = 7/8 and snr of -8.5db. an adja-cent channel at ?0mhz is added at -25dbm. dvb-s ber performance of 2e-4 shall be maintained for the desired signal. gc2 may be adjusted for best performance. note 7 : guaranteed by design and characterization at t a = +25?. note 8 : see table 16 for crystal esr requirements. max2112 4 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications 3.5 3.4 3.3 3.2 3.1 89 90 91 92 93 94 95 96 97 9888 3.0 3.6 supply current vs. supply voltage supply voltage (v) supply current (ma) max2112 toc01 t a = -40 c t a = +25 c t a = +85 c standby mode supply current vs. supply voltage supply voltage (v) supply current (ma) max2112 toc02 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 t a = -40 c t a = +85 c t a = +25 c supply current vs. baseband filter cutoff frequency max2112 toc03 baseband filter cutoff frequency (mhz) supply current (ma) 36 28 32 24 20 16 12 8 86 88 90 92 94 96 98 100 102 104 84 44 0 hd3 vs. v out max2112 toc04 v out (v p-p ) baseband 3rd-order harmonic (dbc) 3.0 2.5 2.0 1.5 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10-60 1.0 3.5 quadrature phase vs. lo frequency lo frequency (mhz) quadrature phase ( ) max2112 toc05a 900 1200 1500 1800 2100 2400 86.5 87.5 88.5 89.5 90.5 91.5 92.5 93.5 t a = +85 c f baseband = 10mhz t a = +25 c t a = -40 c quadrature magnitude matching vs. lo frequency max2112 toc05b lo frequency (mhz) quadrature magnitude matching (db) 2100 1800 1500 1200 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 -0.8 900 2400 t a = +85 c t a = +25 c f baseband = 10mhz t a = -40 c quadrature phase vs. baseband frequency max2112 toc06a baseband frequency (mhz) quadrature phase ( ) 16 12 8 4 87.5 88.5 89.5 90.5 91.5 92.5 93.586.5 02 0 t a = +85 c t a = +25 c f lo = 925mhz t a = -40 c quadrature magnitude matching vs. baseband frequency max2112 toc06b baseband frequency (mhz) quadrature magnitude matching (db) 16 12 8 4 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 -0.8 02 0 t a = +85 c t a = +25 c f lo = 925mhz t a = -40 c baseband filter frequency response max2112 toc07 baseband frequency (mhz) baseband output level (db) 60 40 20 -60 -50 -30-40 -20 -10 0 -80 -70 08 0 typical operating characteristics (max2112 evaluation kit: v cc = +3.3v, t a = +25?, baseband output frequency = 5mhz; v gc1 = +1.2v, default register settings except bbg[3:0] = 1011.) max2112 maxim integrated 5 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications typical operating characteristics (continued) (max2112 evaluation kit: v cc = +3.3v, t a = +25?, baseband output frequency = 5mhz; v gc1 = +1.2v, default register settings except bbg[3:0] = 1011.) baseband filter highpass frequency response max2112 toc08 baseband frequency (mhz) baseband output level (db) 1000 -10 -8 -4-6 -2 0 2 -14 -12 100 10,000 programmed f -3db frequency vs. measured f -3db frequency max2112 toc09 programmed f -3db frequency (mhz) measured f -3db frequency (mhz) 40 20 15 25 30 35 510 5 10 2015 25 3530 40 45 0 04 5 lpf[7:0] = 12 + (f -3db - 4mhz)/290khz baseband filter 3db frequency vs. temperature temperature ( c) baseband gain error at f -3db (db) max2112 toc10 -40-200 20406080 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 normalized to t a = +25 c input power vs. v gc1 v gc1 (v) input power (dbm) max2112 toc11 0.5 1.0 1.5 2.0 2.5 3.0 -80 -70 -60 -50 -40 -30 -20 -10 0 10 adjust bbg[3:0] for 1v p-p baseband output withp in = -75dbm and v gc1 = 0.5v t a = -40 c t a = +85 c t a = +25 c noise figure vs. frequency frequency (mhz) noise figure (db) max2112 toc12 900 1100 1300 1500 1700 1900 2100 2300 7.5 8.0 8.5 9.0 9.5 10.0 10.5 t a = +25 c t a = +85 c adjust bbg[3:0] for 1v p-p baseband output with p in = -75dbm and v gc1 = 0.5v t a = +70 c noise figure vs. input power max2112 toc13 input power (dbm) noise figure (db) -20 -30 -40 -50 -60 -70 2010 30 40 50 60 70 0 -80 0 -10 adjust bbg[3:0] for 1v p-p baseband output withp in = -75dbm and v gc1 = 0.5v. f lo = 1500mhz out-of-band iip3 vs. input power max2112 toc14 input power (dbm) out-of-band iip3 (dbm) -20 -30 -40 -50 -60 -70 -10-20 0 10 20 30 -30 -80 0 -10 see note 4 on page 4 for conditions in-band iip3 vs. input power max2112 toc15 input power (dbm) in-band iip3 (dbm) -20 -30 -40 -50 -60 -70 -30-50 -40 -10-20 0 10 20 30 -60 -80 0 -10 see note 3 on page 4 for conditions iip2 vs. input power max2112 toc16 input power (dbm) iip2 (dbm) -20 -30 -40 -50 -60 -70 0 10 3020 40 50 60 -10 -80 0 -10 see note 5 on page 4 for conditions max2112 6 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications input return loss vs. frequency max2112 toc17 frequency (mhz) input return loss (db) 2025 1800 1350 1575 1125 -20 -15 -10 -5 0 -25 900 2250 v gc1 = 2.7v v gc1 = 0.5v phase noise at 10khz offset vs. channel frequency channel frequency (mhz) phase noise at 10khz offset (dbc/hz) max2112 toc18 925 1115 1305 1495 1685 1875 2065 2255 -105 -100 -95 -90 phase noise vs. offset frequency max2112 toc19 offset frequency (hz) phase noise (dbc/hz) 1.0e+05 1.0e+04 -120 -110 -100 -90 -130 1.0e+03 1.0e+06 f lo = 1800mhz vco: kv vs. vtune vtune (v) kv (mhz/v) max2112 toc21 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200 250 300 350 400 450 sub-band 23 sub-band 12 sub-band 0 lo leakage vs. lo frequency lo frequency (mhz) lo leakage (dbm) max2112 toc20 925 1175 1425 1675 1925 2175 -90 -85 -80 -75 -70 measured at rf input typical operating characteristics (continued) (max2112 evaluation kit: v cc = +3.3v, t a = +25?, baseband output frequency = 5mhz; v gc1 = +1.2v, default register settings except bbg[3:0] = 1011.) max2112 maxim integrated 7 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications pin description pin name function 1 vcc_rf2 dc power supply for lna. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possib l e to the pi n. d o not shar e capaci tor gr ound vi as w ith other g r ound connections. 2 vcc_rf1 dc power supply for lna. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possib l e to the pi n. d o not shar e capaci tor gr ound vi as w ith other g r ound connections. 3 gnd ground. connect to board? ground plane for proper operation. 4 rfin wideband 75 rf input. connect to an rf source through a dc-blocking capacitor. 5 gc1 rf gain-control input. high-impedance analog input with a 0.5v to 2.7v operating range.v gc1 = 0.5v corresponds to the maximum gain setting. 6 vcc_lo dc power supply for lo generation circuits. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 7 vcc_vco dc power supply for vco circuits. connect to a +3.3v low-noise supply. bypass to gnd with a 1nfcapacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 8 vcobyp internal vco bias bypass. bypass to gnd with a 100nf capacitor connected as close as possible tothe pin. do not share capacitor ground vias with other ground connections. 9 vtune high-impedance vco tune input. connect the pll loop filter output directly to this pin with as short of aconnection as possible. 10 gndtune ground for vtune. connect to the pcb ground plane. 11 gndsyn ground for synthesizer. connect to the pcb ground plane. 12 cpout c h ar g e - p um p o u tp u t . c o n n e c t t h i s o u t p u t t o t he p l l l o o p fi l t e r i n p u t w i t h th e s h or t e s t c o n n e ct i o n p o ss i b l e . 13 vcc_syn dc power supply for synthesizer circuits. connect to a +3.3v low-noise supply. bypass to gnd with a1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 14 xtal crystal-oscillator interface. use with an external parallel-resonance-mode crystal through a series 1nfcapacitor. see the typical application circuit . 15 refout crystal-oscillator buffer output. a dc-blocking capacitor must be used when driving external circuitry. 16 vcc_dig dc power supply for digital logic circuits. connect to a +3.3v low-noise supply. bypass to gnd with a1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. 17 qout+ 18 qout- quadrature baseband differential output. ac-couple with 47nf capacitors to the demodulator input. 19 iout+ 20 iout- in-phase baseband differential output. ac-couple with 47nf capacitors to the demodulator input. 21 idc+ 22 idc- i-channel baseband dc offset correction. connect a 47nf ceramic chip capacitor from idc- to idc+. 23 qdc+ 24 qdc- q- c hannel baseb and d c o ffset c or r ecti on. c onnect a 47nf cer am i c chi p cap aci tor fr om qd c - to qd c + . 25 vcc_bb dc power supply for baseband circuits. connect to a +3.3v low-noise supply. bypass to gnd with a 1nf capacitor connected as close as possible to the pin. do not share capacitor ground vias with other ground connections. max2112 8 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications detailed description register description the max2112 includes 12 user-programmable regis- ters and 2 read-only registers. see table 1 for register configurations. the register configuration of table 1 shows each bit name and the bit usage information for all registers. note that all registers must be written after and no earlier than 100? after the device is powered up. pin description (continued) pin name function 26 sda 2-wire serial-data interface. requires 1k pullup resistor to v cc . 27 scl 2-wire serial-clock interface. requires 1k pullup resistor to v cc . 28 addr address. must be connected to either ground (logic 0) or supply (logic 1). ep exposed paddle. solder evenly to the board? ground plane for proper operation. table 1. register configuration msb lsb data byte reg number r eg i st er n a m e r ea d / wr it e r eg a d d r ess d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 1 n-divider msb write 0x00 frac 1 n[14] n[13] n[12] n[11] n[10] n[9] n[8] 2 n-divider lsb write 0x01 n[7] n[6] n[5] n[4] n[3] n[2] n[1] n[0] 3 charge pump write 0x02 cpmp[1] 0 cpmp[0] 0 cplin[1] 0 cplin[0] 1 f[19] f[18] f[17] f[16] 4 f-divider msb write 0x03 f[15] f[14] f[13] f[12] f[11] f[10] f[9] f[8] 5 f-divider lsb write 0x04 f[7] f[6] f[5] f[4] f[3] f[2] f[1] f[0] 6 xtal divider r-divider write 0x05 xd[2] xd[1] xd[0] r[4] r[3] r[2] r[1] r[0] 7 pll write 0x06 d24 cps icp x x x x x 8 vco write 0x07 vco[4] vco[3] vco[2] vco[1] vco[0] vas adl ade 9 lpf write 0x08 lpf[7] lpf[6] lpf[5] lpf[4] lpf[3] lpf[2] lp f[ 1] lpf[0] 10 control write 0x09 stby x pwdn 0 x bbg[3] bbg[ 2] bbg[ 1] bbg[ 0] 11 shutdown write 0x0a x pll 0 div 0 vco 0 bb 0 rfmix 0 rfvga 0 fe 0 12 test write 0x0b cptst[2] 0 cptst[1] 0 cptst[0] 0 x turbo 1 ld m u x[ 2] 0 ld m u x[ 1] 0 ld m u x[ 0] 0 13 status byte-1 read 0x0c por vasa vase ld x x x x 14 status byte-2 read 0x0d v c os br[4] v c os br[3] v c os br[2] v c os br[1] v c os br[0] ad c[ 2] ad c[ 1] ad c[ 0] x = don? care. 0 = set to 0 for factory-tested operation. 1 = set to 1 for factory-tested operation. max2112 maxim integrated 9 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications table 2. n-divider msb register bit name bit location (0 = lsb) default function frac 7 1 users must program to 1 upon powering up the device. n[14:8] 6? 0000000 sets the most significant bits of the pll integer-divide number (n). n canrange from 19 to 251. table 3. n-divider lsb register bit name bit location (0 = lsb) default function n[7:0] 70 00100011 sets the least significant bits of the pll integer-divide numb er. n can range from 19 to 251. table 4. charge-pump register bit name bit location (0 = lsb) default function cpmp[1:0] 7? 00 charge-pump minimum pulse width. users must program to 00 uponpowering up the device. cplin[1:0] 5? 00 controls charge-pump linearity. users must program to 01 upon powering upthe device. f[19:16] 3? 0010 s ets the 4 m ost si g ni fi cant b i ts of the p ll fr acti onal d i vi d e num b er . d efaul t val ue i s f = 194,180 d eci m al . table 5. f-divider msb register bit name bit location (0 = lsb) default function f[15:8] 7? 11110110 s ets the m ost si g ni fi cant b i ts of the p ll fr acti onal - d i vi d e num b er ( f) . d efaul t val ue i s f = 194,180 d eci m al . table 6. f-divider lsb register bit name bit location (0 = lsb) default function f[7:0] 7? 10000100 s ets the l east si g ni fi cant b i ts of the p ll fr acti onal - d i vi d e num b er ( f) . d efaul t val ue i s f = 194,180 d eci m al . table 7. xtal buffer and reference divider register bit name bit location (0 = lsb) default function xd[2:0] 7? 000 sets the crystal-divider setting.000 = divide by 1. 001 = divide by 2. 011 = divide by 3. 100 = divide by 4. 101 through 110 = all divide values from 5 (101) to 7 (110). 111 = divide by 8. r[4:0] 4? 00001 sets the pll reference-divider (r) number. users must program to 00001upon powering up the device. 00001 = divide by 1; other values are not tested. max2112 10 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications table 8. pll register bit name bit location (0 = lsb) default function d24 7 1 vco divider setting.0 = divide by 2. use for lo frequencies 1125mhz. 1 = divide by 4. use for lo frequencies < 1125mhz. cps 6 1 charge-pump current mode.0 = charge-pump current controlled by icp bit. 1 = charge-pump current controlled by vco autoselect (vas). icp 5 0 charge-pump current.0 = 600? typical. 1 = 1200? typical. x 4? x don? care. table 9. vco register bit name bit location (0 = lsb) default function vco[4:0] 7? 11001 c ontr ol s w hi ch v c o i s acti vated w hen usi ng m anual v c o p r og r am m i ng m od e. thi s al so ser ves as the star ti ng p oi nt for the v c o autosel ecti on ( v as ) m od e. vas 2 1 vco autoselection (vas) circuit. 0 = disable vco selection must be programmed through i 2 c. 1 = enable vco selection controlled by autoselection circuit. adl 1 0 enables or disables the vco tuning voltage adc latch when the vcoautoselect mode (vas) is disabled. 0 = disables the adc latch. 1 = latches the adc value. ade 0 0 enables or disables vco tuning voltage adc read when the vco autoselectmode (vas) is disabled. 0 = disables adc read. 1 = enables adc read. table 10. lowpass filter register bit name bit location (0 = lsb) default function lpf[7:0] 7? 01001011 sets the baseband lowpass filter 3db corner frequency. f -3db = 4mhz + (lpf[7:0] dec - 12) x 290khz. default value equates to f -3db = 22.27mhz typical. max2112 maxim integrated 11 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications table 11. control register bit name bit location (0 = lsb) default function stby 7 0 software standby control.0 = normal operation. 1 = d i sab l es the si g nal p ath and fr eq uency synthesi zer l eavi ng onl y the 2- w i r e b us, cr ystal osci l l ator , x talou t b uffer , and x talou t b uffer d i vi d er acti ve. x 6 x don? care. pwdn 5 0 factory use only.0 = normal operation; other value is not tested. x 4 x don? care. bbg[3:0] 3-0 0000 baseband gain setting (1db typical per step).0000 = minimum gain (0db, default). 1111 = maximum gain (15db typical). table 12. shutdown register bit name bit location (0 = lsb) default function x 7 x don? care. pll 6 0 pll enable.0 = normal operation. 1 = shuts down the pll. value not tested. div 5 0 divider enable.0 = normal operation. 1 = shuts down the divider. value not tested. vco 4 0 vco enable.0 = normal operation. 1 = shuts down the vco. value not tested. bb 3 0 baseband enable.0 = normal operation. 1 = shuts down the baseband. value not tested. rfmix 2 0 rf mixer enable.0 = normal operation. 1 = shuts down the rf mixer. value not tested. rfvga 1 0 rf vga enable.0 = normal operation. 1 = shuts down the rf vga. value not tested. fe 0 0 front-end enable.0 = normal operation. 1 = shuts down the front-end. value not tested. max2112 12 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications table 13. test register bit name bit location (0 = lsb) default function cptst[2:0] 75 000 charge-pump test modes. 000 = normal operation (default). x 4 x dont care. turbo 3 0 charge-pump fast lock. users must program to 1 after powering up the device. ldmux[2:0] 20 000 refout output. 000 = normal operation. other values are not tested. table 14. status byte-1 register bit name bit location (0 = lsb) function por 7 power-on reset status.0 = chip status register has been read with a stop condition since last power-on. 1 = power-on reset (power cycle) has occurred. default values have been loaded in registers. vasa 6 indicates whether vco autoselection was successful.0 = indicates the autoselect function is disabled or unsuccessful vco selection. 1 = indicates successful vco autoselection. vase 5 status indicator for the autoselect function.0 = indicates the autoselect function is active. 1 = indicates the autoselect process is inactive. ld 4 pll lock detector. turbo bit must be programmed to 1 for valid ld reading.0 = unlocked. 1 = locked. x 3:0 don? care. table 15. status byte-2 register bit name bit location (0 = lsb) function vcosbr[4:0] 7-3 vco band readback. adc[2:0] 2-0 vas adc output readback.000 = out of lock. 001 = locked. 010 = vas locked. 101 = vas locked. 110 = locked. 111 = out of lock. max2112 maxim integrated 13 downloaded from: http:///
2-wire serial interface the max2112 uses a 2-wire i 2 c-compatible serial inter- face consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate bidirectional communication between the max2112 and the master at clock frequencies up to 400khz. the master initiates a data transfer on the bus and generates the scl sig- nal to permit data transfer. the max2112 behaves as a slave device that transfers and receives data to and from the master. sda and scl must be pulled high with external pullup resistors (1k ? or greater) for proper bus operation. pullup resistors should be referenced tothe max2112? v cc . one bit is transferred during each scl clock cycle. aminimum of nine clock cycles is required to transfer a byte in or out of the max2112 (8 bits and an ack/nack). the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi-tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high. acknowledge and not-acknowledge conditions data transfers are framed with an acknowledge bit(ack) or a not-acknowledge bit (nack). both the mas- ter and the max2112 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. to generate a not-acknowledge condition, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the bus master must reattempt communication at a later time. slave address the max2112 has a 7-bit slave address that must besent to the device following a start condition to initi- ate communication. the slave address is internally pro- grammed to 1100000. the eighth bit (r/ w ) following the 7-bit address determines whether a read or writeoperation occurs. the max2112 continuously awaits a start condition followed by its slave address. when the device recog- nizes its slave address, it acknowledges by pulling the sda line low for one clock period; it is ready to accept or send data depending on the r/ w bit (figure 1). the write/read address is c0/c1 if addr pin is con-nected to ground. the write/read address is c2/c3 if addr pin is connected to v cc . write cycle when addressed with a write command, the max2112allows the master to write to a single register or to multi- ple successive registers. a write cycle begins with the bus master issuing a start condition followed by the seven slave address bits and a write bit (r/ w = 0). the max2112 issues an ack if the slave address byte is successfully received.the bus master must then send to the slave the address of the first register it wishes to write to (see table 1 for register addresses). if the slave acknowledges the address, the master can then write one byte to the regis- ter at the specified address. data is written beginning with the most significant bit. the max2112 again issues an ack if the data is successfully written to the register. the master can continue to write data to the successive internal registers with the max2112 acknowledging each successful transfer, or it can terminate transmission by issuing a stop condition. the write cycle does not termi- nate until the master issues a stop condition. complete, direct-conversion tuner for dvb-s2 applications scl 1 234567 1100000 89 r/w ack slave address s sda figure 1. max2112 slave address byte with addr pin connected to ground write device address r/ w ack write register address ack write data to register 0x00 ack write data to register 0x01 ack write data to register 0x02 ack start 1100000 0 0x00 0x0e 0xd8 0xe1 stop figure 2. example: write registers 0 through 2 with 0x0e, 0xd8, and 0xe1, respectively. max2112 14 maxim integrated downloaded from: http:///
read cycle when addressed with a read command, the max2112allows the master to read back a single register, or mul- tiple successive registers. a read cycle begins with the bus master issuing a start condition followed by the 7 slave address bits and a write bit (r/ w = 0). the max2112 issues an ack if the slave address byte is successfully received. the busmaster must then send the address of the first register it wishes to read (see table 1 for register addresses). the slave acknowledges the address. then, a start condi- tion is issued by the master, followed by the 7 slave address bits and a read bit (r/ w = 1). the max2112 issues an ack if the slave address byte is successfullyreceived. the max2112 starts sending data msb first with each scl clock cycle. at the 9th clock cycle, the master can issue an ack and continue to read succes- sive registers, or the master can terminate the transmis- sion by issuing a nack. the read cycle does not terminate until the master issues a stop condition. figure 3 illustrates an example in which registers 0 through 2 are read back. application information the max2112 downconverts rf signals in the 925mhz to2175mhz range directly to the baseband i/q signals. the devices are targeted for digital dbs tuner applications. rf input the rf input of the max2112 is internally matched to75 ? . only a dc-blocking capacitor is needed. see the typical application circuit . rf gain control the max2112 features a variable-gain low-noise ampli-fier providing 73db of rf gain range. the voltage con- trol (vgc) range is 0.5v (minimum attenuation) to 2.7v (maximum attenuation). baseband variable-gain amplifier the receiver baseband variable-gain amplifiers provide15db of gain control range programmable in 1db steps. the vga gain can be serially programmed through the spi interface by setting bits bbg[3:0] in the control register. baseband lowpass filter the max2112 includes a programmable on-chip 7th-order butterworth filter. the filter -3db corner fre- quency can be adjusted from approximately 4mhz to 40mhz by programming the lpf[7:0] register using the following equation: lpf[7:0] dec = (f -3db - 4mhz)/0.29mhz + 12, where f -3db is in units of mhz. total device supply current depends on the filter bwsetting. see supply current vs. baseband filter cutoff frequency in the typical operating characteristics for more information. dc offset cancellation the dc offset cancellation is required to maintain thei/q output dynamic range. connecting an external capacitor between idc+ and idc- forms a highpass fil- ter for the i channel and an external capacitor between qdc+ and qdc- forms a highpass filter for the q chan- nel. keep the value of the external capacitor less than 47nf to form a typical highpass corner of 250hz. xtal oscillator the max2112 contains an internal reference oscillator,reference output divider, and output buffer. all that is required is to connect a crystal through a series 1nf capacitor. to minimize parasitics, place the crystal and series capacitor as close as possible to pin 14 (xtal pin). see table 16 for crystal (xtal) esr (equivalent series resistance) requirements. vco autoselect (vas) the max2112 includes 24 vcos. the local oscillatorfrequency can be manually selected by programming the vco[4:0] bits in the vco register. the selected vco is reported in the status byte-2 register (see table 15). complete, direct-conversion tuner for dvb-s2 applications device address r / w 1100000 register address 00000000 0 s t ar t s t ar t a c k a c k reg 02 data xxxxxxxx s t o p n a c k reg 00 data xxxxxxxx a c k reg 01 data xxxxxxxx a c k a c k device address r / w 1100000 1 figure 3. example: receive data from read registers table 16. maximum crystal esr requirement esr max ( ) xtal frequency (mh) 80 12 < f xtal 14 60 14 < f xtal 30 max2112 maxim integrated 15 downloaded from: http:///
alternatively, the max2112 can be set to autonomouslychoose a vco by setting the vas bit in the vco regis- ter to logic-high. the vas routine is initiated once the f-divider lsb register word (reg 5) is loaded. in the event that only the n-divider register or f-divider msb word is changed, the f-divider lsb word must also be loaded last to initiate the vco autoselect function. the vco value programmed in the vco[4:0] register serves as the starting point for the auto-matic vco selection process. during the selection process, the vase bit in the status byte-1 register is cleared to indicate the autoselection function is active. upon successful completion, bits vase and vasa are set and the vco selected is reported in the status byte-2 register (see table 15). if the search is unsuccessful, vasa is cleared and vase is set. this indi- cates that searching has ended but no good vco has been found, and occurs when trying to tune to a frequen- cy outside the vco? specified frequency range. refer to the max2112/max2120 vco autoselect (vas) application note for more information. 3-bit adc the max2112 has an internal 3-bit adc connected tothe vco tune pin (vtune). this adc can be used for checking the lock status of the vcos. table 17 summarizes the adc output bits and the vco lock indication. the vco autoselect routine only selects a vco in the ?as locked?range. this allows room fora vco to drift over temperature and remain in a valid ?ocked?range. the adc must first be enabled by setting the ade bit in the vco register. the adc reading is latched by a sub- sequent programming of the adc latch bit (adl = 1). the adc value is reported in the status byte-2 register (see table 15). standby mode the max2112 features normal operating mode andstandby mode using the i 2 c interface. setting a logic- high to the stby bit in the control register puts thedevice into standby mode, during which only the 2- wire-compatible bus, the crystal oscillator, the xtal buffer, and the xtal buffer divider are active. in all cases, register settings loaded prior to entering shutdown are saved upon transition back to active mode. default register values are provided for the user? convenience only. it is the user? responsibility to load all the registers no sooner than 100? after the device is powered up. layout considerations the max2112 ev kit serves as a guide for pcb layout.keep rf signal lines as short as possible to minimize losses and radiation. use controlled impedance on all high-frequency traces. for proper operation, the exposed paddle must be soldered evenly to the board? ground plane. use abundant vias beneath the exposed paddle for maximum heat dissipation. use abundant ground vias between rf traces to minimize undesired coupling. bypass each v cc pin to ground with a 1nf capacitor placed as close as possible to the pin. complete, direct-conversion tuner for dvb-s2 applications table 17. adc trip points and lock status adc[2:0] lock status 000 out of lock 001 locked 010 vas locked 101 vas locked 110 locked 111 out of lock max2112 16 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications vtune gndsyn cpout vcc_syn xtal vcobyp scl vcc_bb qdc- addr qdc+ idc- rfin gc1 vcc_lo + iout+ qout-vcc_dig gndtune sda 19 17 16 3 5 18 4 6 refout 15 7 vcc_rf1 iout- 20 2 vcc_rf2 21 idc+ 1 26 24 23 10 12 25 11 13 22 14 27 9 28 8 max2112 interface logic and control dc offset correction lpf bw control div2 /div4 ep frequency synthesizer qout+ v cc v cc v cc baseband outputs serial-clock input serial-data input/output v cc v gc v cc v cc gnd vcc_vco rf input v cc typical application circuit max2112 maxim integrated 17 downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications chip information process: bicmos package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw-ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tqfn-ep t2855+3 21-0140 90-0023 max2112 18 maxim integrated downloaded from: http:///
complete, direct-conversion tuner for dvb-s2 applications revision history revision number revision date description pages changed 0 8/07 initial release 1 12/07 corrected errors in data sheet 1?, 9?6 2 5/10 corrected errors in function cells of tables 8 and 10, corrected formula in baseband lowpass filter section 11, 15 max2112 downloaded from: http:/// 0d[lp,qwhjudwhg5lr5reohv6dq-rvh&$86$ maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. ? maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc.

▲Up To Search▲

Price & Availability of MAX2112CTIT

	To Download MAX2112CTIT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .